Many portable and battery-operated devices are designed so that embedded SRAMs in the devices will operate at low voltages. A small percentage of SRAM bits in these devices may be prone to malfunction due to aging of the circuit in which the SRAM resides. Furthermore, the malfunctions may change based on consumer usage patterns (e.g., utilizing a significant amount of power) and the environment in which the system operations (e.g., temperature of the surrounding area, etc.).
One approach to mask errors based on these malfunctions in a SRAM is to use Error Correction Code (ECC). ECC is used to protect against different physical phenomena that may negatively affect systems that need to function without outages. The implementation of ECC for memory designs is expensive and may create additional problems related to timing.
A SRAM product that leaves the factory without defects may later experience intermittent failures or glitches due to the aging or environment. Masking such failures or glitches in the functioning of a SRAM allows it to function correctly throughout its lifetime despite the presence of a small number of errors in the SRAM. It is important for mobile products, such as laptops, where consumers do not generally upgrade systems, to be able to operate in the presence of such errors.
One mechanism to assist a product in operating in the presence of errors in SRAM is to utilize redundancy in the SRAM to mask failures. In some conventional designs of SRAM, redundancy is introduced at manufacturing into large SRAMs to mask manufacturing errors and increase yield. However, such redundancy may not be able to be reconfigured during the lifetime of the SRAM. Also, many designs have hundreds of small SRAMs, and configuring redundancy at manufacturing to mask failures due to aging and the environment may be impossible in some cases.